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continuous rate 12.3 mb/s to 2.7 gb/s clock and data recovery ic with integrated limiting amp data sheet adn2812 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2004 C 2012 analog devices, inc. all rights reserved. f eatures serial data input: 12.3 mb/s to 2.7 gb/s exceeds sonet requirements for jitter transfer/ generation/tolerance quantizer sensitivity: 6 mv typical adjustable slice level: 100 mv patented clock recovery architecture loss of signal (los) detect ran ge: 3 mv to 15 mv independent slice level adjust and los detector no reference clock required loss of lock indicator i 2 c interface to access optional features single - supply operation: 3.3 v low power: 750 mw typical 5 mm 5 mm 32 - lead lfcsp a pplications s onet oc - 1/ oc - 3/ oc - 12/ oc - 48 and all associated fec rates fibre channel, 2 fibre channel, gbe, hdtv wdm transponders regenerators/repeaters test equipment broadband cross - connects and routers general d escription the adn2812 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 mb/s to 2.7 gb/s. the adn2812 auto - matically locks to all data rates without the need for an external reference clock or programming. all sonet jitter re quirements are met, including jitter transfer, jitter generation, and jitter tolerance. all specifications are quoted for ?40c to +85c ambient temperature, unless otherwise noted. this device, together with a pin diode and a tia preamplifier, can impleme nt a highly integrated, low cost, low power fiber optic receiver. the receiver front end , loss of signal (los) detector circuit indicates when the input signal level has fallen below a user - adjustable threshold. the los detect circuit has hysteresis to pre vent chatter at the output. the adn2812 is available in a compact 5 mm 5 mm 32 - lead lead frame chip scale package (lfcsp) . f unctional b lock d iagram 2 04228-001 slicep/n lo l dat aoutp/n los thradj clkoutp/n 2 vcc vee cf1 cf2 pin nin vref quantizer vco phase shifter phase detect frequenc y detect los detect dat a re-timing loo p fi l ter loo p fi l ter refclkp/n (optional) 2 figure 1.
adn2812 data sheet rev. e | page 2 of 28 t able of c ontents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functio nal block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 jitter s pecifications ....................................................................... 4 output and timing specifications ............................................. 5 absolute maximum ratings ............................................................ 6 thermal characteristics .............................................................. 6 esd caution .................................................................................. 6 timing characteristics ..................................................................... 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 i 2 c interface timing and inte rnal register description ........... 10 terminology .................................................................................... 12 input sensitivity and input overdrive ..................................... 12 single - ended vs. differential .................................................... 12 los response time ................................................................... 12 jitter specifications ......................................................................... 13 jitter generation ......................................................................... 13 jitter transfer .............................................................................. 13 jitter tolerance ............................................................................ 13 theory of operation ...................................................................... 14 functional description .................................................................. 16 frequency acquisition ............................................................... 16 limiting amplifier ..................................................................... 16 slice adjust .................................................................................. 16 los detector .............................................................................. 16 lock detector operation .......................................................... 16 harmonic detector .................................................................... 17 squelch mode ............................................................................. 17 i 2 c interface ................................................................................ 18 reference clock (optional) ...................................................... 18 applications information .............................................................. 21 pcb design guidelines ............................................................. 21 dc - coupled application .......................................................... 23 coarse data rate readback look - up table ............................... 24 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 26 revision history 3/12 rev. d to rev. e updat ed outline dimensions ....................................................... 26 changes to ordering guide .......................................................... 26 5/10 rev. c to rev. d changes to figure 4, table 5 ........................................................... 8 changes to figure 24 ...................................................................... 21 2/09 rev. b to rev. c updated outline dimensions ....................................................... 26 changes to ordering guide .......................................................... 26 6/07 rev. a to rev. b change s to table 1 ............................................................................ 3 c hange s to table 6 .......................................................................... 11 change s to ltr mode description ............................................. 19 changes to ordering guide .......................................................... 26 11/04 rev. 0 to rev. a change to specification .................................................................... 3 updated outline dimensions ....................................................... 26 changes to using the reference clock to lock onto data section .............................................................................................. 19 3/04 revision 0: initial versi on
data sheet adn2812 rev. e | page 3 of 28 specifications t a = t min to t max , vcc = v min to v max , vee = 0 v, c f = 0.47 f, slicep = slicen = vee, input data pa ttern: prbs 2 23 ? 1, unless otherwise noted. table 1 . parameter conditions min typ max unit quantiz er dc characteristics input voltage range @ pin or nin, dc - coupled 1.8 2.8 v peak -to - peak differential input pin C nin 2.0 v input common - mode level dc - coupled (see figure 28, figure 29, and figure 30) 2.3 2.5 2.8 v differential input sensitivity 2 23 ? 1 pr bs, ac - coupled, 1 ber = 1 10 C 10 10 6 mv p -p input overdrive (see figure 12) 5 3 mv p -p input offset 500 v input rms noise ber = 1 x 10 C10 290 v rms quantizer ac characteristics data rate 12.3 2700 mb/s s11 @ 2.5 ghz ? 15 db input resistance differential 100 ? input capacitance 0.65 pf quantizer slice adjustment gain slicep C slicen = 0.5 v 0.08 0.1 0.125 v/v differential control voltage input slicep C slicen ? 0.95 +0.95 v control volta ge range dc level @ slicep or slicen vee 0.95 v slice threshold offset 1 mv loss of signal detect (los) loss of signal detect range r thresh = 0 ? (see figure 5 ) 11 13 17 mv r thresh = 100 k ? 1.5 3 4.0 mv hysteresis ( electrical) oc -48 r thresh = 0 ? 5.6 6 7.2 db r thresh = 100 k ? 3.7 6 8.4 db oc -1 r thresh = 0 ? 5.6 6 7.2 db r thresh = 10 k ? 2.0 4 6.7 db los assert time dc - coupled 2 500 ns los de assert time dc - coupled 2 450 ns loss of lock detect (lol) vco frequency error for lol assert with respect to nominal 1000 ppm vco frequency error for lol de assert with respect to nominal 250 ppm lol response time 12.3 mb/s 4 ms oc -12 1.0 s oc -48 1.0 s acquisition time lock to data mode oc -48 1.3 ms oc -12 2.0 ms oc -3 3.4 ms oc -1 9.8 ms 12.3 mb/s 40.0 ms optional lock to refclk mode 10.0 ms
adn2812 data sheet rev. e | page 4 of 28 parameter conditions min typ max unit data rate readback accuracy coarse readback see ta ble 14 10 % fine readback in addition to refclk accuracy data rate 20 mb/s 200 ppm data rate > 20 mb/s 100 ppm power supply voltage 3.0 3.3 3.6 v power supply current 235 259 ma operating temperature range C 40 +85 c 1 pin and nin should be differentially driven and ac - coupled for optimum sensitivity. 2 when ac - coupled, the los assert and deassert time is domi nated by the rc time constant of the ac coupling capacitor and the 50 ? input termination of the adn2812 input stage. jitter sp ecifications t a = t min to t max , vcc = v min to v max , vee = 0 v, c f = 0.47 f, slicep = slicen = vee, input data p attern: prbs 2 23 ? 1, unless otherwise noted. table 2 . parameter conditions min typ max unit phase - locked loop charact eristics jitter transfer bw oc -48 490 670 khz oc -12 71 108 khz oc -3 23 35 khz jitter peaking oc -48 0 0.03 db oc -12 0 0.03 db oc -3 0 0.03 db jitter generation oc - 48, 12 khz to 20 mhz 0.001 0.002 ui rms 0.02 0.037 ui p -p oc - 12, 1 2 khz to 5 mhz 0.001 0.002 ui rms 0.01 0.019 ui p -p oc - 3, 12 khz to 1.3 mhz 0.001 0.002 ui rms 0.01 0.011 ui p -p jitter tolerance oc - 48, 2 23 ? 1 prbs 600 hz 70 92 ui p -p 6 khz 19 45 ui p -p 100 khz 3.8 5 ui p -p 1 mhz 0.75 1 ui p - p 20 mhz 0.4 0.6 ui p -p oc - 12, 2 23 ? 1 prbs 30 hz 1 100 ui p -p 300 hz 1 44 ui p -p 25 khz 2.5 ui p -p 250 khz 1 1.0 ui p -p oc - 3, 2 23 ? 1 prbs 30 hz 1 50 ui p -p 300 hz 1 24 ui p -p 6500 hz 3.5 ui p -p 65 khz 1.0 ui p -p 1 jitter tolerance of the adn2812 at these jitter frequencies is better than what the test equipment is able to measure.
data sheet adn2812 rev. e | page 5 of 28 output and timing sp ecifications table 3 . parameter conditions min typ max unit cml ouput characteristics (clkoutp/ clkout n, dataoutp/ dataout n) single - ended output swing v se (see figure 3 ) 300 350 600 mv different ial output swing v diff (see figure 3 ) 600 700 1200 mv output high voltage v oh vcc v output low voltage v ol vcc ? 0.6 vcc ? 0.35 vcc ? 0.3 v cml ou t puts timing rise time 20% to 80% 95 112 ps fall time 80% to 20% 95 123 ps setup time t s (see figure 2 ), oc -48 150 200 250 ps hold time t h (see figure 2 ), o c -48 150 200 250 ps i 2 c ? interface dc characteristics lvcmos input high voltage v ih 0.7 vcc v input low voltage v il 0.3 vcc v input current v in = 0.1 vcc or v in = 0.9 vcc ? 10.0 +10.0 a output low voltage v ol , i ol = 3.0 ma 0.4 v i 2 c inter face timing see figure 11 sck clock frequency 400 khz sck pulse width high t high 600 ns sck pulse width low t low 1300 ns start condition hold time t hd;sta 600 ns start condition setup time t su;sta 600 ns data setup time t su;dat 100 ns data hold time t hd; dat 300 ns sck/sda rise/fall time t r / t f 20 + 0.1 cb 1 300 ns stop condition setup time t su; sto 600 ns bus free time b etween a stop and a start t buf 1300 ns refclk characteristics optional lock to refclk mode input voltage range @ refclkp or refclkn v il 0 v v ih vcc v minimum differential input drive 100 mv p -p reference frequency 12.3 200 mhz required accuracy 100 ppm lvttl dc input characteristics input high volta ge v ih 2.0 v input low voltage v il 0.8 v input high current i ih , v in = 2.4 v 5 a input low current i il , v in = 0.4 v ? 5 a lvttl dc output characteristics output high voltage v oh , i oh = ? 2.0 ma 2.4 v output low voltage v ol , i ol = +2.0 ma 0.4 v 1 cb = total capacitance of one bus line in pf. if mixed with hs mode devices, fast er fall - times are allowed (see table 6 ).
adn2812 data sheet rev. e | page 6 of 28 absolute maximum rat ings t a = t min to t max , vcc = v min to v max , vee = 0 v, c f = 0.47 f, slicep = slicen = vee, unless otherwise noted. table 4 . parameter rating supply voltage (vcc) 4.2 v minimum input voltage (all inputs) vee ? 0.4 v maximum input voltage (all inputs) vcc + 0.4 v maximum junction temperature 125c storage temperature ? 65c to +150c lead temperature (soldering 10 s) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditio ns above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characterist ics thermal resistance 32- lfcsp, 4 - layer board with exposed paddle soldered to vee ja = 28c/w. esd caution
data sheet adn2812 rev. e | page 7 of 28 timing characteristi cs 04228-002 clkout p dat aoutp/n t s t h figure 2 . output timing 04228-003 out p outn out p ? outn 0v v se v cm l v se v diff figure 3 . single- ended vs. differential output specifications
adn2812 data sheet rev. e | page 8 of 28 pin configuratio n and function descr iptions 04228-004 vcc 1 vcc 2 vre f 3 pin 1 indic a t or t op view (not to scale) 24 vcc 23 vee 22 los 21 sd a 32 vcc 20 sck 19 saddr5 18 vcc 17 vee thradj 9 refclk p 10 refclkn 1 1 vcc 12 vee 13 cf2 14 cf1 15 lo l 16 nin 4 pin 5 slice p 6 slicen 7 vee 8 31 vcc 30 vee 29 d at aout p 28 d at aoutn 27 squelch 26 clkout p 25 clkoutn adn2812* * there is an exposed p ad on the bot t om of the p ackage th a t must be connected t o gnd. figure 4 . pin configuration table 5 . pin function descriptions pin no. mnemonic type 1 description 1 vcc ai connect to vcc. 2 vcc p power for limamp, los. 3 vref ao inter nal vref voltage. decouple to gnd with a 0.1 f capacitor. 4 nin ai differential data input. cml. 5 pin ai differential data input. cml. 6 slicep ai differential slice level adjust input. 7 slicen ai differential slice level adjust input. 8 vee p gnd for limamp, los. 9 thradj ai los threshold setting resistor. 10 refclkp di differential refclk input. 12.3 mhz to 200 mhz. 11 refclkn di differential refclk input. 12.3 mhz to 200 mhz. 12 vcc p vco power. 13 vee p vco gnd. 14 cf2 ao frequency loop ca pacitor. 15 cf1 ao frequency loop capacitor. 16 lol do loss of lock indicator. lvttl active high. 17 vee p fll detector gnd. 18 vcc p fll detector power. 19 saddr5 di slave address bit 5. 20 sck di i 2 c clock input. 21 sda di i 2 c data input. 22 los do loss of signal detect output. active high. lvttl. 23 vee p output buffer, i 2 c gnd. 24 vcc p output buffer, i 2 c power. 25 clkoutn do differential recovered clock output. cml. 26 clkoutp do differential recovered clock output. cml. 27 squelch di di sable clock and data outputs. active high. lvtll. 28 dataoutn do differential recovered data output. cml. 29 dataoutp do differential recovered data output. cml. 30 vee p phase detector, phase shifter gnd. 31 vcc p phase detector, phase shifter power. 32 vcc ai connect to vcc. exposed pad pad p connect to gnd. works as a heat sink. 1 p = power, ai = analog input, ao = analog output, di = digital input, do = digital output.
data sheet adn2812 rev. e | page 9 of 28 typical performance characteristics 04228-005 16 14 12 1 10 100 r thresh () 1k 10k 100k 10 8 6 4 2 tri p point (mv p-p) figure 5 . los comparator trip point programming 04228-006 1000 1 10 100 1k 10k 100k 1m 10m jitter frequenc y (hz) 100m 0.1 1 10 100 jitter amplitude (ui) adn2812 t olerance sonet requirement mask sonet objective mask equipment limit figure 6 . typical measured jitter tolerance oc - 48
adn2812 data sheet rev. e | page 10 of 28 i 2 c interface timing a nd internal register description 04228-007 1 a5 0 0 0 0 0 x msb = 1 set b y pin 19 0 = wr 1 = rd sla ve address [6:0] r/w ctrl. figure 7 . slave address configuration 04228-008 s sla ve addr, lsb = 0 (wr) a(s) a(s) a(s) dat a sub addr a(s) p dat a figure 8. i 2 c write data transfer 04228-009 s s = s t art bit p = s t op bit a(s) = acknowledge b y sl a ve a(m) = acknowledge b y master a(m) = lack of acknowledge b y master s sla ve addr, lsb = 0 (wr) sla ve addr, lsb = 1 (rd) a(s) a(s) sub addr a(s) dat a a(m) dat a p a(m) figure 9. i 2 c read data transfer 04228-010 st art bit s st op bit p ack ack wr ack d0 d7 a0 a7 a5 a6 sladdr[4...0] sla ve address sub address dat a sub addr[6:1] dat a[6:1] sck sda figure 10 . i 2 c data transfer timing 04228-0 1 1 t buf sda s s p s sck t f t low t r t f t hd;s t a t hd;d a t t su;d a t t high t su;s t a t su;s t o t hd;s t a t r figure 11 . i 2 c port timing diagram
data sheet adn2812 rev. e | page 11 of 28 table 6 . internal register map 1 reg . name r/w address d7 d6 d5 d4 d3 d2 d1 d0 freq0 r 0x 0 0 msb lsb freq1 r 0x 0 1 msb lsb freq2 r 0x 0 2 0 msb lsb rate r 0x 0 3 coarse_rd[8] msb coarse data rate readback coarse_rd[1] misc r 0x 0 4 x x los status static lol lol status data rate measure complete x coarse_ rd[0] lsb ctrla w 0x 0 8 f ref range data rate/div_f ref ratio measure data rate lock to reference ctrla_rd r 0x0 5 readback ctrla c ontents ctrlb w 0x 0 9 config lol reset misc[4] system reset 0 reset misc[2] 0 0 0 ctrlb_rd r 0 x0 6 readback ctrlb c ontents ctrlc w 0x11 0 0 0 0 0 config lo s squelch mode 0 1 all writeable registers default to 0x00. table 7 . miscellaneous register, misc los status static lol lol status data r ate measurement complete coarse rate readback lsb d7 d6 d5 d4 d3 d2 d1 d0 x x 0 = no lo ss of signal 0 = waiting for next lol 0 = locked 0 = measuring data rate x coarse_rd[0] 1 = loss of signal 1 = static lol until reset 1 = acquiring 1 = measurement complete table 8 . control register, ctrla 1 f ref range data r a te/div_f ref ratio mea sure data r ate lock to reference d7 d6 d5 d4 d3 d2 d1 d0 0 0 12.3 mhz to 25 mhz 0 0 0 0 1 set to 1 to measure data rate 0 = lock to input data 0 1 25 mhz to 50 mhz 0 0 0 1 2 1 = lock to reference clock 1 0 50 mhz to 100 mhz 0 0 1 0 4 1 1 100 mhz to 200 mhz n 2 n 1 0 0 0 256 1 where div_f ref is the divided down reference referred to the 12.3 mhz to 25 mhz band (see the reference clock (optional) section). table 9 . contr ol register, ctrlb config lol reset misc[4] system reset reset misc[2] d7 d6 d5 d4 d3 d2 d1 d0 0 = lol pin normal operation 1 = lol pin is static lol write a 1 followed by 0 to reset misc[4] write a 1 followed by 0 to reset adn2812 set to 0 write a 1 followed by 0 to reset misc[2] set to 0 set to 0 set to 0 table 10 . control register, ctrlc config los squelch mode d7 d6 d5 d4 d3 d2 d1 d0 set to 0 set to 0 set to 0 set to 0 set to 0 0 = active high los 0 = squelch c lk and data set to 0 1 = active low los 1 = squelch clk or data
adn2812 data sheet rev. e | page 12 of 28 terminology input sensitivity an d input overdrive sensitivity and overdrive specifications for the quantizer involve offset voltage, gain, and noise. the relationship between the log ic output of the quantizer and the analog voltage input is shown in figure 12 . for sufficiently large positive input voltage, the output is always at logic l evel 1 and, similarly for negative inputs, the output is always at logic l e vel 0. however, the output transitions between logic l evel 1 and logic l evel 0 are not at precisely defined input voltage levels but occur over a range of input voltages. within this range of input voltages, the output might be either 1 or 0, or it migh t even fail to attain a valid logic state. the width of this zone is determined by the input voltage noise of the quantizer. the center of the zone is the quantizer input offset voltage. input overdrive is the magni - tude of signal required to guarantee th e correct logic level with 1 10 ?10 confidence level. 04228-012 noise output input (v p-p) offset overdrive sensitivit y (2 ? overdrive) 1 0 figure 12 . input sensitivity and input overdrive single - ended vs. differenti al ac coupling is typically used to drive the inputs to the quan - tizer. the inputs are internally dc biased to a common - mode potent ial of ~2.5 v. driving the adn2812 single - ended and observing the quantizer input with an oscilloscope probe at the point i ndicated in figure 13 show a binary signal with an averag e value equal to the common - mode potential and ins tantaneous values both above and below the average value. it is convenient to measure the peak - to - peak amplitude of this signal and call the minimum required value the quantizer sensitivity. referring to figure 13 , because both pos itive and negative offsets need to be accommodated, the sensitivity is twice the overdrive. the adn2812 quantizer typically has 6 mv p - p sensitivity. 04228-013 scope probe pin n 2.5v vref adn2812 quantizer + ? 10mv p-p vref figure 13 . single - ended sensitivity measurement while d riving the adn2812 diffe rentially (see figure 14 ), sen - sitivity seems to improve from observing the quantizer input with an oscilloscope probe. this is an illusion caused by the use of a single - ended probe. a 5 mv p - p signal appears to drive the adn2812 q uantizer. however, the single - ended probe measures only half the signal. the true quantizer i nput signal is twice this value because the other quantizer input is a complementary signal to the signal being observed. 04228-014 scope probe pin n 2.5v vref quantizer + ? nin 5mv p-p vref 5mv p-p vref figure 14 . di fferential sensitivity measurement los response time loss of signal ( los ) response time is the delay between removal of the input signal and indication of los at the los output, pin 22. when the inputs are dc - coupled, the los assert time of the ad2812 is 500 ns typical ly and the deassert time is 400 ns typically. in practice, the time constant produced by the ac coupling at the quantizer input and the 50 ? on - chip input termination determines the los response time.
data sheet adn2812 rev. e | page 13 of 28 jitter specification s the adn2812 cdr is designed to achieve the best bit - error - rate (ber ) performance and exceeds the jitter transfer, generatio n, and tolerance specifications proposed for sonet/sdh equip - ment defined in the telcordia technologies gr - 253- core document . jitter is the dynamic d isplacement of digital signal edges from their long - term average positions, measured in unit intervals (ui), where 1 ui = 1 bit period. jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge. jitter on the recovered cl ock causes jitter on the retimed data. the following sections briefly summarize the specifications of jitter generation, jitter transfer, and jitter tolerance in accordance with the gr - 253- core from telcordia for the optical interface at the equipment lev el and the adn2812 performance with respect to those specifications. jitter generation the jitter generation specification limits the amount of jitter that can be generated by the device with no jitter and wander applied at the input. for oc - 48 devices, th e band - pass filter has a 12 khz high - pass cutoff frequency with a roll - off of 20 db/decade and a low - pass cutoff frequency of at least 20 mhz . the jitter generated must be less than 0.01 ui rms and must be less than 0.1 ui p - p. jitter transfer the jitter t ransfer function is the ratio of the jitter on the output signal to the jitter applied on the input signal vs. the frequency. this parameter measures the limited amount of the jitter on an input signal that can be transferred to the output signal (see figure 15). 04228-015 0.1 accep t able range f c jitter frequenc y (khz) slope = ?20db/decade jitter gain (db) figure 15 . jitter transfer curve jitter tolerance the jitter tolerance is defined as the peak - to - peak amplitude of the sinusoidal jitter applied on the input signal, which causes a 1 db power pena lty. this is a stress test to ensure that no addi - tional penalty is incurred under the operating conditions (see figure 16). 04228-016 15.00 1.50 0.15 f 0 f 1 f 2 f 3 f 4 jitter frequenc y (khz) slope = ?20db/decade input jitter amplitude (ui p-p) figure 16 . sonet jitter tolerance mask
adn2812 data sheet rev. e | page 14 of 28 theory of operation the adn2812 is a delay - and phase - locked loop circuit for clock recovery and data retiming from an nrz encoded data stream. the phase of the input data signal is tracked by two separate feedback loops that share a common control voltage. a high speed delay - locked loop pat h uses a voltage controlled phase shifter to track the high frequency components of input jitter. a separa te phase control loop, comprised of the vco, tracks the low frequency components of input jitter. the initial frequency of the vco is set by yet a thi rd loop, which compares the vco frequency with the input data frequency and sets the coarse tuning voltage. the jitter tracking phase - locked loop controls the vco by the fine - tuning control. the delay - and phase - loops together track the phase of the input data signal. for example, when the clock lags input data, the phase detector drives the vco to a higher frequenc y and also increases the delay through the phase shifter; both these actions serve to reduce the phase error between the clock and data. the fas ter clock picks up phase, while the delayed data loses phase. because the loop filter is an integrator, the static phase error is driven to zero. another view of the circuit is that the phase shifter implements the zero required for frequency compensation of a second - ord er , phase - locked loop. this zero is placed in the feedback path and, thus, does not appear in the closed - loop transfer function. jitter peaking in a conventional second - order phase - locked loop is caused by the presence of this zero in the cl osed - loop transfer function. because this circuit has no zero in the closed - loop transfer, jitter peaking is minimized. the delay - and phase - loops together simultaneously provide wide - band jitter accommodation and narrow - band jitter filter - ing. the lineari zed block diagram in figure 17 shows that the jitter transfer function, z(s)/x(s), is a second - order low - pass providing excellent filtering. note that the jitter transfer has no zero, unlike an ordinary second - order phase - locked lo op. this means that the main pll loop has virtually zero jitter peaking (see figure 18 ), making this circuit ideal for signal regenerator applications, where jitter peaking in a cascade of regenerators can contribute to hazardous j itter accumulation. the error transfer, e(s)/x(s), has the same high - pass form as an ordinary phase - locked loop. this transfer function is free to be optimized to give excellent wide - band jitter accommodation because the jitter transfer function, z(s)/x(s) , provides the narrow - band jitter filtering. 04228-017 x(s) z(s) recovered clock e(s) input dat a d/sc psh o/s 1/n d = phase detec t or gain o = vco gain c = loo p integr a t or psh = phase shifter gain n = divide r a tio = 1 cn do s 2 + n psh o s + 1 z(s) x(s) jitter transfer function = s 2 s 2 d psh c s + + do cn e(s) x(s) tracking error transfer function figure 17 . pll/dll architecture adn2812 z(s) x(s) 04228-018 frequenc y (khz) jitter peaking in ordina r y pl l jitter gain (db) o n psh d psh c figure 18 . jitter response vs. conventional pll the delay - and phase - loops contribute to overall jitter accom - modation. at l ow frequencies of input jitter on the data signal, the integrator in the loop filter provides high gain to track large jitter amplitudes with small phase error. in this case, the vco is frequency modulated and jitter is tracked as in an ordinary phase - loc ked loop. the amount of low frequency jitter that can be tracked is a function of the vco tuning range. a wider tuning range gives larger accommodation o f low frequency jitter. the internal loop control voltage remains small for small phase errors, so the phase shifter remains close to the center of its range and thus contributes little to the low frequency jitter accommodation.
data sheet adn2812 rev. e | page 15 of 28 at medium jitter frequencies, the gain and tuning range of the vco are not large enough to track input jitter. in this case, the vco control voltage becomes large and saturates, and the vco frequency dwells at one extreme of its tuning range or the other. the size of the vco tuning range, therefore, has only a small effect on the jitter accommodation. the delay - locked loop control voltage is now larger, so the phase shifter takes on the burden of tracking the input jitter. the phase shifter range, in ui, can be seen as a broad plateau on the jitter tolerance curve. the phase shifter has a minimum range of 2 ui at all data rates. the gain of the loop integrator is small for high jitter frequencies so that larger phase differences are needed to make the loop control voltage big enough to tune the range of the phase shifter. large phase errors at high jitter frequencies cannot be tolera ted. in this region, the gain of the integrator determines the jitter accommodation. because the gain of the loop integra - tor declines linearly with frequency, jitter accommodation is lower with higher jitter frequency. at the highest frequencies, the loop gain is very small, and little tuning of the phase shifter can be expected. in this case, jitter accommodation is determined by the eye opening of the input data, the static phase error, and the residual loop jitter generation. the jitter accommodation is roughly 0.5 ui in this region. the corner frequency between the declining slope and the flat region is the closed loop bandwidth of the delay - locked loop, which is roughly 3 mhz at oc - 48.
adn2812 data sheet rev. e | page 16 of 28 functional descripti on frequency acquisitio n the adn2812 acquir es frequency from the data over a range of data frequencies from 12.3 mb/s to 2.7 gb/s. the lock detector circuit compares the frequency of the vco and the frequency of the incoming data. when these frequencies differ by more than 1000 ppm, lol is asserted . this initiates a frequency acquisition cycle. the vco frequency is reset to the bottom of its range, which is 12.3 mhz. the frequency detector then compares this vco frequency and the incoming data frequency and increments the vco frequency, if necessar y. initially, the vco frequency is incremented in large steps to aid fast acquisi - tion. as the vco frequency approaches the data frequency, the step size is reduced until the vco frequency is within 250 ppm of the data freq uency, at which point lol is de as serted. once lol is de asserted, the frequency - locked loop is turned off. the pll/dll pulls in the vco frequency the rest of the way until the vco frequency equals the data frequency. the frequency loop requires a singl e external capacitor between cf2 an d c f 1 ( pin 14 and pin 15 ) . a 0.47 f 20%, x7 r cerami c chip capacitor with < 10 na leakage current is recommended. leakage current of the capacitor can be calculated by dividing the maximum voltage across the 0.47 f capacitor, ~3 v, by the insulation resista nce of the capacitor. the insulation resistance of the 0.47 f capacitor should be greater than 300 m ? . limiting amplifier the limiting amplifier has differential inputs (pin/nin), which are internally terminated with 50 ? to an on - chip voltage reference (vref = 2.5 v typically). the inputs are typically ac ? coupled externally, although dc coupling is pos sible as long as the input common - mode voltage remains above 2.5 v (see figure 28, figure 29 , and figure 30 ). input offset is factory trimmed to achiev e better than 6 mv typical s ensitivity with minimal drift. the limiting amplifier can be driven differentially or single - ended. slice adjust the quantizer slicing level can be offset by 100 mv to mitigate the effect of amplified spontaneous emission (ase) noise or duty cycle distort ion by applying a differential voltage input of up to 0.95 v to the slicep/ slice n inputs. if no adjustment of the slice level is needed, slicep/ slice n should be tied to vee. the gain of the slice adjustment is ~0.1 v/v. los detector the receiver front - end los detector circuit detects when the input signal level has fallen below a user - adjustable threshold. the threshold is set with a single external resistor from pin 9 ( thradj ) to vee. the los comparator trip point - vs. - resistor value is illustrated in figure 5 . if the input level to the adn2812 drops below the programmed los threshold, the output of the los detector, los ( pin 22 ) , is asserted to a logic 1. the los detectors response time is ~500 ns b y design but is dominated by t he rc time constant in ac - coupled applications. the los pin defaults to active high. however, by setting bit ctrlc[2] to 1, the los pin is configured as active low. typically, 6 db of electrical hysteresis is designed into the los detector to prevent chat ter on the los pin. this means that if the input level drops below the programmed los threshold causing the los pin t o assert, the los pin is not de asserted until the input level increases to 6 db (2) above the los threshold (see f igure 19). 04228-019 hysteresis los output input leve l los threshold t input vo lt age (v diff ) figure 19 . los detector hysteresis the los detector and the slice level adjust can be used simul - taneously on the adn2812. this means that any offset added to the input signal by the slice adjust pins does not affect the los detectors measurement of the absolute input level. lock detector operat ion the lock detector on the adn2812 has three modes of ope ration: normal mode, refclk mode, and static lol mode. normal mode in normal mode, the adn2812 is a continuous rate c dr that locks onto any data rate from 12.3 mb/s to 2.7 gb/s without the use of a reference clock as an acquisition aid. in this mode, the lock detector monitors the frequency difference between the vco and t he input data frequ ency and de asserts the loss of lock signal appearing on lol ( pin 16 ) when the vco is within 250 ppm of the data frequency. this enables the d/pll, which pulls the vco frequency in the remaining amount and also acquires phase lock. once locked, if the input frequency error exceeds 1000 ppm (0.1%) , the loss of lock signal is re asserted and control returns to the frequency loop, which begins a new frequency acquisition starting at the lowest point in the vco operating range, 12.3 mhz. the lol pin remains asserted until the vco locks onto a valid input data stream to within 250 ppm frequency error. this hysteresis is shown in figure 20.
data sheet adn2812 rev. e | page 17 of 28 04228-020 lo l 0 ?250 250 1000 f vco error (ppm) ?1000 1 figure 20 . transfer function of lol lol detector operation using a reference clock (refclk mode ) in refc lk mode, a reference clock is used as an acquisition aid to lock the adn2812 vco. lock to reference mode is enabled by setting ctrla[0] to 1. the user also needs to write to the ctrla[7:6] and ctrla[5:2] bits in order to set the reference frequency range and the divide ratio of the data rate with respect to the reference frequency. for more details, see the reference clock (optional) section. in this mode, the lock detector monitors the difference in frequency between the divide d down vco and the divided down reference clock. the loss of lock signal, which a ppears on lol ( pin 16 ) , is de as - serted w hen the vco is within 250 ppm of the desired frequenc y. this enables the d / pll, which pulls the vco frequency in the remaini ng amount with respect to the input data and also acquires phase lock. once locked, if the input frequency error exceeds 1000 ppm (0.1%), the loss of lock signal is reasserted and control returns to the freq uency loop, which re acquires with respect to the reference clock. the lol pin remains asserted until the vco frequency is within 250 ppm of the desired frequency. this hysteresis is shown in figure 20. static lol mode the adn2812 implements a static lol feature, which indicates if a loss o f lock condition has ever occurred and remains asserted , even if t he adn2812 regains lock, until the static lol bit is manu - ally reset. the i 2 c register bit, misc[4], is the static lol bit. if there is ever an occurrence of a loss of lock condition, this b it is internally asserted to logic high. the misc[4] bit remains hig h even after the adn2812 has re acquired lock to a new data rate. this bit can be reset by writing a 1 followed by 0 to i 2 c register bit ctrlb[6]. once re set, the misc[4] bit remains de asse rted until another loss of lock condition occurs. writing a 1 to i 2 c register bit ctrlb[7] causes the lol pin (pin 16) to become a static lol indicator. in this mode, the lol pin mirrors the contents of the misc[4] bit and has the function ality described in the previous paragraph. the ctrlb[7] bit defaults to 0. in this mode, the lol pin operates in the normal operating mode , that is, it is asserted only when the adn2812 is in acquisition mode an d deasserts when the adn2812 has re acquired lock. harmonic detector the adn2812 provides a harmonic detector, which detects whether the input data has changed to a lower harmonic of the data rate onto which the vco is currently locked. for example, if the input data instantaneously changes from oc - 48, 2.488 gb/s, to an oc - 12, 622.080 mb/s bit stream, this could be perceived as a valid oc - 48 bit stream because the oc - 12 data pattern is exactly 4 slower than the oc - 48 pattern. so, if the change in data rate is instantaneous, a 101 pattern at oc - 12 would be per - ceive d by the adn2812 as a 111100001111 pattern at oc - 48 . if the change to a lower harmonic is instantaneous, a typical cdr could remain locked at the higher data rate. the adn2812 implements a harmonic detector that automati - cally identifies whether the input data has switched to a lower harmonic of the data rate onto which the vco is currently locked. when a harmonic is identified, the lol pin is asserted and a new frequency acquisition is initiated. the adn2812 automatically locks onto the new data rate, and the lol pin is deasserted. however, the harmonic detector does not detect higher har - monics of the data rate. if the input data rate switches to a higher harmonic of the data rate that the vco is currently locked onto, the vco loses lock, the lol pin is a sserted, and a new frequency acquisition is initiated. the adn2812 auto matically locks onto the new data rate. the time to detect lock to harmonic is 16,384 ( t d /) where: 1/ t d is the new data rate. for example, if the data rate is switched from oc - 48 to oc - 12, then t d = 1/622 mhz. is the data transition density. most coding schemes seek to ensure that = 0.5, for example, prbs, 8b/10b. when the adn2812 is pla ced in lock to reference mode, the harmonic detector is disabled. squelch mode two squelch modes are available with the adn2812. squelch dataout and clkout mode is selected when ctrlc[1] = 0 (default mode). in th is mode, when the squelch input ( pin 27 ) is driven to a ttl high state, both the clock and data outputs are set to the zero state to suppress downstream processing. if the squelch function is not required, pin 27 should be tied to vee. squelch dataout or clkout mode is selected when ctrlc[1] is 1. in this mode, when the squelch input is driven to a high state, the dataout pins are squelched. when the squelch input is driven to a low state, the clkout pins are squelched. this is especially useful in repeater appli - cations, where the recovered clock may not be needed.
adn2812 data sheet rev. e | page 18 of 28 i 2 c interface the adn2812 supports a 2 - wire, i 2 c - compatible, serial bus driving multiple peripherals. two inputs, serial data (sda) and serial clock (sck), carry information between any devices connected to the bus. each slave d evice is recognized by a unique address. the adn2812 has two possible 7 - bit slave addresses for both read and write operations. the msb of the 7 - bit slave address is factory programmed to 1. b5 of the slave address is set by pin 19, saddr5. slave address b its [4:0] are defaulted to all 0s. the slave address consists of the 7 msbs of an 8 - bit word. the lsb o f the word sets either a read or write operation (see figure 7 ). logic 1 corresponds to a read operation, while logic 0 corresp onds to a write operation. to control the device on the bus, the following protocol must be followed. t he master initiates a data transfer by establish ing a start condition, defined by a high to low transition on sda while sck remains high. this indicates that an address/data stream follows . all peripherals respond to the start condition and shift the next eight bits (the 7 - bit address and the r/w bit). the bits are tra nsferred from msb to lsb. the peripheral that recogn izes the transmitted address respond s by pulling the data line low during the ninth clock pulse. this is known as an acknowledge bit. all other devices withdraw from the bus at this point and maintain an idle condition. the idle condition is where the device monitors the sda and sck lines wa iting for the start condition and correct transmitted address. the r/w bit determines the direction of the data. logic 0 on the lsb of the first byte means that the master writes information to the peripheral. logic 1 on the lsb of the first byte means th at the master reads information from the peripheral. the adn2812 acts as a standard slave device on the bus. the data on the sda pin is 8 bits long supporting the 7 - bit addresses plus the r/w bit. the adn2812 has 8 subaddresses to enable the user - accessibl e internal registers (see table 1 through table 7 ). therefore, it interprets the first byte as the device address and the second byte as the starting subaddress. autoincrement mode is supported, allowing data to be read from or written to the starting subaddress and each subsequent address without manually addressing the subsequent subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique subaddress register on a one - by - one basis without updating all registers. stop and start conditions can be detected at any stage of the data transfer. if these conditions are asserted out of sequence with normal read and write operations, they cause an imme - diate jump to the idle condition. during a given sck high period, the user should issue one start condition, one stop condition, or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the adn2812 does not issue an acknowledge and returns to the idle condition. if the user exceeds the highest subaddress while reading back in autoincrement mode, the highest subad dress register contents continue to be output until the master device issues a no acknowledge. this indic a tes the end of a read. in a no acknowledge condition, the sdata line is not pulled low on the ninth pulse. see figure 8 and figure 9 for sample write and read data transfers and figu re 10 for a more detailed timing diagram. reference clock (opt ional) a reference clock is not required to perform clock and data recovery with the adn2812. however, support for an optional reference clock is provided. the reference clock can be driven dif ferentially or single - ended. if the reference clock is not being used, refclkp should be tied to vcc, and refclkn can be left floating or tied to vee (the inputs are internally terminated to vcc/2). see figure 21 through figure 23 for sample configurations. the refclk input buffer accepts any differential signal with a peak - to - peak differential amplitude of greater than 100 mv (for example, lvpecl or lvds) or a standard single - ended low voltage ttl input, providing maximum system flexibility. phase noise and duty cycle of the reference clock are not critical, and 100 ppm accuracy is sufficient. 04228-021 100k vcc/2 100k adn2812 refclk p 10 1 1 refclkn buffer figure 21 . differential refclk configuration 04228-022 100k vcc/2 100k adn2812 refclk p out refclkn buffer vcc clk osc figure 22 . si ngle - ended refclk configuration 04228-023 100k : vcc/2 100k : adn2812 refclk p 10 1 1 nc refclkn buffer vcc figure 23 . no refclk configuration
data sheet adn2812 rev. e | page 19 of 28 the two uses of the reference clock are mutually exclusive. the reference clock can be used either as an acquisition aid fo r the adn2812 to lock onto data or to measure the frequency of the incoming data to within 0.01%. (there is the capability to meas - ure the data rate to approximately 10 % without the use of a reference clock.) the modes are mutually exclusive because, in the first use, the user knows the exac t data rate and wants to force the part to lock onto only that data rate; in the second use, the user does not know the data rate and wants to measure it. lock to reference mode is enabled by writing a 1 to i 2 c register bit ctrla[0]. fine data rate readbac k mode is enabled by writing a 1 to i 2 c register bit ctrla[1]. writing a 1 to both of these bits at the same time causes an indeterminate state and is not supported. using the reference clock to lock onto data writing ctrl a[0] = 1 puts the adn2812 into l ock - t o - refclk (ltr) m ode. in this mode, the adn2812 locks onto a fre - quency derived from the reference clock according to the following equation: data rate /2 ctrla[5:2] = refclk /2 ctrla[7:6] the user must know exactly what the data rate is and provide a ref erence clock that is a function of this rate. the adn2812 can still be used as a continuous rate device in this configu - ration, provided that the user has the ability to provide a reference clock that has a variable frequency (see the appli - cation note an - 632). the reference clock can be anywhere between 12.3 mhz and 200 mhz. by default, the adn 2812 expects a reference clock between 12.3 mhz and 25 mhz. if it is between 25 mhz and 50 mhz, 50 mhz and 100 mhz, or 100 mhz and 200 mhz, the user needs to confi gure the adn2812 to use the correct reference frequency range by setting two bits of the ctrla register, ctrla[7:6]. table 11 . ctrla [7:6] settings ctrla[7:6] range (mhz) 00 12.3 to 25 01 25 to 50 10 50 to 100 11 100 to 200 ta ble 12 . ctrla[5:2] settings ctrla[5:2] ratio 0000 1 0001 2 n 2 n 1000 256 the user can specify a fixed integer multiple of the reference clock to lock onto using ctrla[5:2], where ctrla is set to the data rate/div_f ref and whe re div_f ref represents the divided - down reference referred to the 12.3 mhz to 25 mhz band. for example, if the reference clock frequency is 38.88 m hz and the input data rate is 622.08 mb/s, ctrla[7:6] is set to [01] to give a divided - down reference clock o f 19.44 mhz. ctrla[5:2] is set to [0101], that is, 5, because 622.08 mb/s/19.44 mhz = 2 5 in this mode, if the adn2812 loses lock for any reason, it relocks onto the reference clock and continues to output a stable clock. while the adn2812 is operating in ltr mode, if the user ever c hanges the reference frequency ( the f ref range , ctrla[7:6] or the f ref ratio, ctrla[5:2]), this must be followed by writing a 1 to 0 transition into the ctrlb[5] bit to initiate a new frequency acquisition. a frequency acquisit ion can also be initiated in ltr mode by writing a 0 to 1 transition into ctrla[0] ; however, it is recommende d that a frequency acquisition be initiated by writing a 1 to 0 transition into ctrlb[5] as previously explained. using the reference clock to mea sure data frequency the user can also provide a reference clock to measure the recove red data frequency, in which case the adn2812 compa res the frequency of the incoming data to the incoming reference clock and returns a ratio of th e two frequencies to 0.0 1% (100 ppm). the accuracy error of the reference clock is added to the accuracy of the adn2812 data rate measurement. for example, if a 100 ppm accuracy reference clock is used, the total accuracy of the measurement is within 200 ppm. the reference clock can range from 12.3 m hz to 200 mh z. the adn2812 expects a reference clock between 12.3 mhz and 25 mhz by default. if it is between 25 mhz and 50 mhz, 50 mhz and 100 mhz, or 100 mhz and 200 mhz, the user needs to configure the adn2812 to use the correct reference frequency range by setting two bits of the ctrla register, ctrla[7:6]. using the reference clock to determine the frequency of the incoming data does not affect the manner in which the part locks onto data. in this mode, the reference clock is u sed only to determine the frequency of the data. for this reason, the user does not need to know the data rate to use the reference clock in this manner.
adn2812 data sheet rev. e | page 20 of 28 prior to reading back the data rate using the reference clock, control register ctr la bits[ 7:6 ] bits must be set to the appropriate frequency range with respect to the reference clock being used. a fine data rate readback is then executed as follows: 1. write a 1 to ctrla[1]. this enables the fine data rate measurement capability of the adn2812. this bit is level - sensitive and does not need to be reset to perform subsequent frequency measurements. 2. reset misc[2] by writing a 1 followed by a 0 to ctrlb[3]. this initiates a new data rate measurement. 3. read back misc[2]. if it is 0, the measurement is not comp lete. if it is 1, the measurement is complete and the data rate can be read back on freq[22:0]. the time for a data rate measurement is typically 80 ms. 4. read b ack the data rate from register freq2[6:0], register freq1[7:0], and register freq0[7:0]. use the following equation to determine the data rate: f datarate = ( freq[22:0] f refclk )/2 (14 + sel_rate ) where: freq[22:0] is the reading from freq2[6:0] ( msbyte), freq1[7:0], and freq0[7:0] (lsbyte). f d atar at e is the data rate (mb/s). f refclk is the refclk fr equency (mhz). sel_ r ate is the setting from ctrla[7:6]. table 13. d22 d21...d17 d16 d15 d14...d9 d8 d7 d6...d1 d0 freq2[6:0] freq1[7:0] freq0[7:0] for example, if the reference clock frequency is 32 mhz, sel_rate = 1, because the ctrla[7:6] setting is [01] and the reference frequency fall s into the 25 mhz to 50 mhz range. assume for this example that th e input data rate is 2.488 gb/s (oc - 48). after following s tep 1 through step 4, the value that is read back on freq[22:0] = 0x26e0 10, which is equal to 2.5477 10 6 . plugging this value into the equation yields ( ) ( ) gb/s 488 . 2 2 / 6 e 32 6 e 5477 . 2 ) 1 14 ( = + if subsequent frequency measurements are required, ctrla[1] should remain set to 1. it does not need to be reset. the meas - urement process is reset by writing a 1 followed by a 0 to ctrlb[3]. this initiates a new data rate measurement. follow step 2 through step 4 to read back the new data rate. note that a data rate readback is valid only if lol is low. if lol is high, the data rate readback is invalid . additional features available via the i 2 c interface coarse data rate readback the data rate can be read back over the i 2 c interface to approxi - mately 10% without the need of an external reference clock. a 9 - bit register, coarse_rd[8:0], can be re ad bac k when lol is de asserted. the 8 msbs of this register are the contents of th e rate[7:0] register. the lsb of the coarse_rd register is bit misc[0]. table 14 provides coarse data rate readback to within 10%. los configuration th e los detector output, los ( pin 22 ), can be configured to be either active high or active low. if ctrlc[2] is set to logic 0 (default ), the los pin is active high when a loss of signal conditio n is detected. writing a 1 to ctrlc[2] configures the los pin to be active low when a loss of signal condition is detected. system reset a frequency acquisition can be initiated by writing a 1 followed by a 0 to the i 2 c register bit ctrlb[5]. this initiates a new frequency acquisition while keeping the adn2812 in the operating mode that it was previously programmed to in register ctrl[a], register ctrl[b], and register ctrl[c].
data sheet adn2812 rev. e | page 21 of 28 applications informa tion pcb design guideline s proper rf pcb design techniques must be used for optimal performance. power supply connections and ground planes use of one low impedance ground plane is recommended. the vee pins should be soldered directly to the ground plane to reduce series inductance. if the ground plane is an internal plane and connections to the ground plane are made through vias, multiple vias can be used in parallel to reduce the series inductance, especially on pin 23, which is the ground return for the output buffers. the exposed pad should be connected to the gnd plane using plugged vias so that solder does not leak th rough the vias during reflow. use of a 10 f electrolytic capacitor between vcc and vee is recommended at the location where the 3.3 v supply enters the pcb. when using 0.1 f and 1 nf ceramic chip capacitors, they should be placed between the ic power sup ply vcc and ve e and as close as possible to the adn2812 vcc pins. if connections to the supply and ground are made through vias, the use of multiple vias in parallel helps to reduce series induc - tance, especially on pin 24, which supplies power to the high speed clkoutp/clkoutn and dataoutp/dataoutn output buffers. refer to the schematic in figure 24 for recom - mended connections. by using adjacent power supply and gnd planes, excellent high frequency decoupling can be realized by us ing close spacing between the planes. this capacitance is given by ( ) pf 88 . 0 a/d c r plane = where: r is the dielectric constant of the pcb material. a is the area of the overlap of power and gnd planes (cm 2 ). d is the separation between planes (mm). for fr - 4, r = 4.4 and 0.25 mm spacing, c ~15 pf/cm 2 . 04228-024 r th nc nc = no connect 1 2 3 4 5 6 7 8 vcc vcc vref nin pin slice p slicen vee vcc transmission lines ? vcc vee los sda sck saddr5 vcc vee vcc vcc vee dat aout p dat aoutn squelch clkout p clkoutn thradj refclk p refclkn vcc vee cf2 cf1 lo l 9 10 1 1 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 exposed p ad tied off t o vee plane with vias clkoutn clkout p dat aoutn dat aout p vcc ti a c in c in 1nf 0.1f 0.1f 10f + 0.1f 1nf vcc vcc vcc c c i 2 c controller 0.1f 1nf 0.1f vcc 1nf 0.1f 0.47f !0 insul a tion resis t ance 1nf figure 24 . typical applications circuit
adn2812 data sheet rev. e | page 22 of 28 transmission lines use of 50 ? transmission lines is required for all high frequency input and output signals to minimize reflections: p in, nin, clkoutp, clkoutn, dataoutp, dataoutn (also refclkp, refclkn, if a high frequency reference clock is used, such as 155 mhz). it is also necessary for the pin/nin input traces to be matched in length and the clkoutp/ clkout n and dataoutp/ dataout n ou tput traces to be matched in length to avoid skew between the differential traces. all high speed cml outputs, clkoutp/ clkout n and dataoutp/ dataout n, also require 100 ? back termination chip resistors connected between the output pin and vcc. these resistors should be placed as close as possible to the output pins. these 100 ? resistors are in parallel with on - chip 100 ? termination resistors to cre ate a 50 ? back termination (see figure 25). the high speed inputs, pin and nin, are internally terminated with 50 ? to an internal reference voltage (see figure 26 ). a 0.1 f is recommended between vref ( pin 3 ) and gnd to provide an ac ground for the inputs. as with any high speed mixed - signal design, take care to keep all high speed digital traces away from sensitive analog nodes. 04228-025 adn2812 0.1f 0.1f 100 100 vcc 100 100 vcc 50 v term v term 50 50 50 figure 25 . typical adn2812 applications circuit 04228-026 c in c in 50 0.1f 50 3k nin pin adn2812 2.5v vref 50 50 ti a vcc figure 26 . adn2812 ac - coupled input configuration soldering guidelines for chip scale package the leads on the 32 - lead lfcsp are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package lead l ength and 0.05 mm wider than the package lead width. the lead should be centered on the pad. this ensures that the solder joint size is maximized. the bottom of the chip scale package has a central exposed pad. the pad on the printed circuit board should b e at least as large as this exposed pad. the user must connect the exposed pad to vee using plugged vias so that solder does not leak through the vias during reflow. this ensures a solid connection from the exposed pad to vee. choosing ac coupling capacito rs ac coupling capacitors at the input s (pin, nin) and output s (dataoutp, dataoutn) of the adn2812 must be chosen such that the device works properly over the full range of data rates used in the application. when choosing the capacitors, the time constant formed with the two 50 ? resistors in the signal path must be considered. when a large number of consecutive identical digits (cids) are applied, the capacitor voltage can droop due to baseline wander (see figure 27 ), causing patt ern - dependent jitter (pdj). the user must determine how much droop is tolerable and choose an ac coupling capacitor based on that amount of droop. the amount of pdj can then be approximated based on the capacitor selection. the actual capacitor value sel ection may require some trade - offs between droop and pdj. for example, a ssuming that 2% droop can be tolerated, then the maximum differential droop is 4%. normalizing to v pp droop = ? v = 0.04 v = 0.5 v pp (1 ? e C t/ ); therefore, = 12 t where: is the rc time constant (c is the ac coupling capacitor, r = 100 ? seen by c). t is the total discharge time, which is equal to n . n is the number of cids. t is the bit period. t he capacitor value can then be calculated by comb ining the equations for and t r nt c / 12 once the capacitor value is selected, the pdj can be approximated as 6 . 0 / 1 5 . 0 r nt/rc pspp e t pdj where: pdj pspp is the amount of pattern - dependent jitter a llowed; < 0.01 ui p - p typical. t r is the rise time, which is equal to 0.22/bw, where bw is ~ 0.7 (bit rate). this expression for t r is accurate only for the inputs. the output rise time for the adn2812 is ~100 ps regardless of data rate.
data sheet adn2812 rev. e | page 23 of 28 04228-027 50 50 pin vref nin c in c out c out v1 c in v1b v2 v2b ti a limam p cdr + ? vcc dat aout p dat aoutn 1 v1 v1b v2 v2b v diff 2 3 4 vref vth adn2812 v diff = v2?v2b vth = adn2812 quantizer threshold notes: 1. during d at a pa tterns with high transition densit y , differentia l dc vo lt age a t v1 and v2 is zero. 2. when the output of the ti a goes t o cid, v1 and v1b are driven t o different dc levels. v2 and v2b discharge t o the vref level, which effective l y introduces a differentia l dc offset across the ac coupling ca p aci t ors. 3. when the burst of d at a s t arts again, the differentia l dc offset across the ac coupling ca p aci t ors is applied t o the input levels causing a dc shift in the differentia l inpu t . this shift is large enough such th a t one of the s ta tes, either high or low depending on the levels of v1 and v1b when the ti a went t o cid, is canceled ou t . the quantizer does not recognize this as a v alid s ta te. 4. the dc offset slow l y discharges unti l the differentia l input vo lt age exceeds the sensitivit y of the adn2812. the quantizer can recognize both high and low s ta tes a t this poin t . figure 27 . example of baseline wander dc - coupled application the inputs to the adn2812 can be dc - coupled. this might be neces sary in burst mode applications, where there are long perio ds of cids, and baseline wander cannot be tolerated. if th e inputs to the adn2812 are dc - coupled, care must be taken not to violate the input rang e and common - mode level require ments of the a dn2812 (see figure 28 through figure 30 ). if dc couplin g is required, a nd the output levels of the tia do not adhere to the levels shown in figure 29 , level shifting and/or an attenuator must be between the tia outputs and the adn2812 inputs. 04228-028 50 0.1f 50 3k nin pin adn2812 2.5v vref 50 50 ti a vcc figure 28 . dc - coupled application 04228-029 pin input (v) v pp = pin ? nin = 2 v se = 10mv a t sensitivit y v se = 5mv min v cm = 2.3v min (dc-coupled) nin figure 29 . minimum allowed dc - coupled input levels 04228-030 pin input (v) v pp = pin ? nin = 2 v se = 2.0v max v se = 1.0v max v cm = 2.3v (dc-coupled) nin figure 30 . maximum allowed dc - coupled input levels
adn2812 data sheet rev. e | page 24 of 28 coarse data rate rea dback look - up table code is the 9 - bit value read bac k from coarse_rd[8:0]. table 14. code f mid 0 5.1934e+06 1 5.1930e+06 2 5.2930e+06 3 5.3989e+06 4 5.5124e+06 5 5.6325e+06 6 5.7612e+06 7 5.8995e+06 8 6.0473e+06 9 6.2097e+06 10 6.3819e+06 11 6.5675e+06 12 6.7688e+06 13 6.9874e+06 14 7.2262e+06 15 7.4863e+06 16 7.4139e+06 17 7.4135e+06 18 7.5606e+06 19 7.7173e+06 20 7.8852e+06 21 8.0633e+06 22 8.2548e+06 23 8.4586e+06 24 8.6784e+06 25 8.9180e+06 26 9.1736e+06 27 9.4481e+06 28 9.7464e+06 29 1.0068e+07 30 1.0417e+07 31 1.0791e+07 32 1.0387e+07 33 1.0386e+07 34 1.0586e+07 35 1.0798e+07 36 1.1025e+07 37 1.1265e+07 38 1.1522e+07 39 1.1799e+07 40 1.2095e+07 41 1.2419e+07 42 1.2764e+07 43 1.3135e+07 44 1.3538e+07 45 1.3975e+07 46 1.4452e+07 47 1.4973e+07 code f mid 48 1.4828e+07 49 1.4827e+07 50 1.5121e+07 51 1.5435e+07 52 1.5770e+07 53 1.6127e+07 54 1.6510e+07 55 1.6917e+07 56 1.7357e+07 57 1.7836e+07 58 1.8347e+07 59 1.8896e+07 60 1.9493e+07 61 2.0136e+07 62 2.0833e+07 63 2.1582e+07 64 2.0774e+07 65 2.0772e+07 66 2.1172e+07 67 2.1596e+07 68 2.2049e+07 69 2.2530e+07 70 2.3045e+07 71 2.3598e+07 72 2.4189e+07 73 2.4839e+07 74 2.5527e+07 75 2.6270e+07 76 2.7075e+07 77 2.7950e+07 78 2.8905e+07 79 2.9945e+07 80 2.9655e+07 81 2.9654e+07 82 3.0242e+07 83 3.0869e+07 84 3.1541e+07 85 3.2253e+07 86 3.3019e+07 87 3.3834e+07 88 3.4714e+07 89 3.5672e+07 90 3.6694e+07 91 3.7792e+07 92 3.8985e+07 93 4.0273e+07 94 4.1666e+07 95 4.3164e+07 code f mid 96 4.1547e+07 97 4.1544e+07 98 4.2344e+07 99 4.3191e+07 100 4.4099e+07 101 4.5060e+07 102 4.6090e+07 103 4.7196e+07 104 4.8378e+07 105 4.9678e+07 106 5.1055e+07 107 5.2540e+ 07 108 5.4150e+07 109 5.5899e+07 110 5.7810e+07 111 5.9890e+07 112 5.9311e+07 113 5.9308e+07 114 6.0485e+07 115 6.1739e+07 116 6.3081e+07 117 6.4506e+07 118 6.6038e+07 119 6.7669e+07 120 6.9427e+07 121 7.1344e+07 122 7.3388e+0 7 123 7.5585e+07 124 7.7971e+07 125 8.0546e+07 126 8.3333e+07 127 8.6328e+07 128 8.3095e+07 129 8.3087e+07 130 8.4689e+07 131 8.6383e+07 132 8.8198e+07 133 9.0120e+07 134 9.2179e+07 135 9.4392e+07 136 9.6757e+07 137 9.9356e+07 138 1.0211e+08 139 1.0508e+08 140 1.0830e+08 141 1.1180e+08 142 1.1562e+08 143 1.1978e+08 code f mid 144 1.1862e+08 145 1.1862e+08 146 1.2097e+08 147 1.2348e+08 148 1.2616e+08 149 1.2901e+08 150 1.3208e+08 151 1.3534e+08 152 1.3885e+08 153 1.4269e+08 154 1.4678e+08 155 1.5117e+08 156 1.5594e+08 157 1.6109e+08 158 1.6667e+08 159 1.7266e+08 160 1.6619e+08 161 1.6617e+08 162 1.6938e+08 163 1.7277e+08 164 1.7640e+08 165 1.8024e+08 166 1.8436e+08 167 1.8878e+08 168 1.9351e+08 169 1.9871e+08 170 2.0422e+08 171 2.1016e+08 172 2.1660e+08 173 2.2360e+08 174 2.3124e+08 175 2.3956e+08 176 2.3724e+08 177 2.3723e+08 178 2.4194e+08 179 2.4695e+08 180 2.5233e+08 181 2.5802e+08 182 2.6415e+08 183 2.7067e+08 184 2.7771e+08 185 2.8538e+08 186 2.9355e+08 187 3.0234e+08 188 3.1188e+08 189 3.2218e+08 190 3.3333e+08 191 3.4531e+08
data sheet adn2812 rev. e | page 25 of 28 code f mid 192 3.3238e+08 193 3.3235e+08 194 3.3876e+08 195 3.4553e+08 196 3.5279e+08 197 3.6048e+08 1 98 3.6872e+08 199 3.7757e+08 200 3.8703e+08 201 3.9742e+08 202 4.0844e+08 203 4.2032e+08 204 4.3320e+08 205 4.4719e+08 206 4.6248e+08 207 4.7912e+08 208 4.7449e+08 209 4.7447e+08 210 4.8388e+08 211 4.9391e+08 212 5.0465e+08 21 3 5.1605e+08 214 5.2831e+08 215 5.4135e+08 code f mid 216 5.5542e+08 217 5.7075e+08 218 5.8711e+08 219 6.0468e+08 220 6.2377e+08 221 6.4437e+08 222 6.6666e+08 223 6.9062e+08 224 6.6476e+08 225 6.6470e+08 226 6.7751e+08 227 6.9106e+08 228 7.0558e+08 229 7.2096e+08 230 7.3743e+08 231 7.5514e+08 232 7.7405e+08 233 7.9485e+08 234 8.1688e+08 235 8.4064e+08 236 8.6640e+08 237 8.9438e+08 238 9.2496e+08 239 9.5825e+08 code f mid 240 9.4898e+08 241 9.4893e+08 242 9.6776e+08 243 9.8782e+08 244 1.0093e+09 245 1.0321e+09 246 1.0566e+09 247 1.0827e+09 248 1.1108e+09 249 1.1415e+09 250 1.1742e+09 251 1.2094e+09 252 1.2475e+09 253 1.2887e+09 254 1.3333e+09 255 1.3812e+09 256 1.3295e+09 257 1.3294e+09 258 1 .3550e+09 259 1.3821e+09 260 1.4112e+09 261 1.4419e+09 262 1.4749e+09 263 1.5103e+09 code f mid 264 1.5481e+09 265 1.5897e+09 266 1.6338e+09 267 1.6813e+09 268 1.7328e+09 269 1.7888e+09 270 1.8499e+09 271 1.9165e+09 272 1.8980e+09 273 1. 8979e+09 274 1.9355e+09 275 1.9756e+09 276 2.0186e+09 277 2.0642e+09 278 2.1132e+09 279 2.1654e+09 280 2.2217e+09 281 2.2830e+09 282 2.3484e+09 283 2.4187e+09 284 2.4951e+09 285 2.5775e+09 286 2.6666e+09 287 2.7625e+09
adn2812 data sheet rev. e | page 26 of 28 outli ne dimensions compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bot t om view top view pin 1 indic a t or 32 9 16 17 24 25 8 exposed pa d pin 1 indic a t or 3.25 3.10 sq 2.95 sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min figure 31 . 32 - lead lead frame chip scale package [lfcsp _ w q ] 5 mm 5 mm bod y , very thin quad (cp - 32 - 7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option a dn2812acpz ? 40c to + 85c 32- lead lfcsp_ w q cp -32-7 adn2812acpz -rl ? 40c to + 85c 32- lead lfcsp_ w q , 13 tape - reel , 5 0 00 pcs cp -32-7 adn2812acpz - rl7 ? 40c to + 85c 32- lead lfcsp_ w q , 7 tape - reel , 1500 pcs cp -32-7 eval - adn2812 ebz evaluation board 1 z = rohs compliant part.
data sheet adn2812 rev. e | page 27 of 28 notes
adn2812 data sheet rev. e | page 28 of 28 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors) . ? 2004 C 2012 analog devices, inc. all rights reserved. trademarks and register ed trademarks are the property of their respective owners. d04228 - 0- 3/12(e)

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